Fully delay and multiple stuck-at fault testable sequential circuit design
Anjela Yu. Matrosova, S. Ostanin, Ekaterina A. Nikolaeva, I. Kirienko · Vestnik Tomskogo gosudarstvennogo universiteta Upravlenie vychislitel naya tekhnika i informatika · 2015
In this paper we show that it is possible to derive a sequential circuit either from a transition table or from a State Transition Graph (STG), so that the sequential circuit has the short test detecting all multiple stuck-at faults at gate poles of the circuit, and delay of each circuit path is detectable Keywords: finite state machine (FSM); state transition graph (STG); path delay faults (PDFs); multiple stuck-at faults; monotonous functions.