A High-Level Synthesis System for Reconfigurable Machine: RM-V
Tomokazu Muroya, Koji Hashimoto, Hirotada Takabayashi, Nobutaka Kuroki, Masahiro Numa · IEEJ Transactions on Electronics Information and Systems · 2000
This paper presents a high-level synthesis system, called RMAC-V (Reconfigurable Machine Application Compiler for RM-V), for applications using SDRAMs implemented on the flexible architecture of RM-V (Re-configurable Machine-V) combining FPGAs and memories. Given an application program written in the C language, RMAC-V produces an RT-level hardware description in VHDL. To reduce the clock counts needed to access memories, RMAC-V introduces two techniques: multi-clock scheduling and preloading row address. Experimental results on Wavelet Transform Engine (WTE) have shown 33% fewer total clock counts than those with conventional method.