Designing of Power Efficient ROM Using LVTTL and Mobile-DDR IO Standard on 28nm FPGA
Tarun Agrawal, Vivek Kumar Srivastava, Anjan Kumar · 2015
This paper contains designing of energy efficient memory circuit using two different IO standard i.e. LVTTL and Mobile-DDR on 28nm (Artix-7) Field Programmable Gate Array. We are using Xilinx ISE simulator version 14.2, Verilog hardware description language and Artix-7 FPGA. The design has been tested at different operating frequencies of Latest Intel processor that are at Intel I-3, Intel I-5 and Intel I-7 to check the compatibility of the design with processors available in the market and to find most efficient IO standard at different operating frequencies.