SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors
Mehdi Sadi, Sukeshwar Kannan, LeRoy Winemberg, Mark Mohammad Tehranipoor · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2016
Speed binning of system-on-chips (SoCs) using conventional Fmax test requires application of complex functional test patterns. Functional workload-based speed binning techniques incur high test-cost in terms of long test-time and complexity in functional test generation, and require high-end automatic test equipment. In this paper, we propose a novel speed binning flow that uses path timing slacks, extracted with robust digital embedded sensor IPs, of selected critical/nearcritical paths. We apply machine learning techniques to model a predictor considering the extracted slacks and the Fmaxvalues from a set of randomly tested die during wafer sort. The trained predictor is used to obtain the Fmaxfor the remaining chips. The proposed flow has been demonstrated in an SoC benchmark circuit at 28 nm technology. For sufficient number of training samples, Fmaxis correctly predicted for 99% of the prediction samples.