High performance implementation of mixing of column and inv mixing of column for AES on FPGA
Priyesh Parikh, Satish S. Narkhede · 2016 International Conference on Computation of Power, Energy Information and Commuincation (ICCPEIC) · 2016
With the scenario of today, everybody using internet, net banking, and online shopping. Nowadays people having smart phone, palm top with latest updated operating system like windows 10, android. These gadgets are using as G.P.S., pocket banking, gaming, notepad, reminder and lot of ways. The most and very important thing is security. To fulfill this important requirement the efficient way is Encryption Decryption algorithm. But another point is speed means algorithm which would be efficient and fast. In order to achieve this requirement, different algorithms have been designed and implemented in the past, but every algorithm possess their own shortcomings with respect to an ASIC or an FPGA implementation. In this paper, I proposed and implemented of a one very useful method for area efficient and high performance for AES by using “Mixing of column and Inverse mixing of column operation” which is the one of the major block of operation in AES to implement the high performance of AES. I SIMULATE and SYNTHESIS on XILINX ISE 14.7 and implemented on VIRTEX 4. It is 100% area efficient; I compared my result with other. With this implementation I given the different methods for s-box and another methods to implement the mixing of column and inverse mixing of column.