Programmable 28nm coprocessor for HEVC/H.265 in-loop filters
Ilkka Hautala, Jani J. Boutellier, Olli Siiven · 2016
High Efficiency Video Coding (HEVC) in-loop filtering includes the deblocking filter (DF) and the sample adaptive offset filter which consume about 20% of the total HEVC de coding time. In this paper a very energy efficient programmable multicore coprocessor for HEVC in-loop filtering is proposed. The coprosessor is placed and routed using leading edge 28nm technology to show that it can be clocked at 1.2 GHz while power consumption is only 207mW including memories. The design is able to filter 101 1080p intra frames per second. The cores can be reprogrammed using a high level language which enables use the high performance coprocessor also for other signal processing algorithms. The proposed coprocessor offers a new alternative between fixed accelerators and general purpose processors for mobile devices in terms of energy efficiency and programmability.