Towards high-level hardware verification using MDGs
Fang Wang · 2007
To tackle the complexity of modern digital systems, the new generation design methodology starts a system design with a description at the system level using a high-level language. This System Level Model (SLM) is then manually refined into Register Transfer Level (RTL) model, which is further automatically synthesized into lower-level design models until the final product is cast. The functional equivalence between SLM and RTL is crucial in this design flow, but there is no automatic verification tool available. Multi-way Decision Diagram (MDG) is a data structure, originally introduced to alleviate the state space problem of formal verification. This paper proposes to develop an MDG based high-level verification system to automatically prove the behavioral equivalence between SLM and RTL. To this end, this paper provides the definition of equivalence between SLM and RTL in MDGs, presents the methodologies of high-level verification using MDGs and outlines the framework of the tool to be developed.