AMBA Interface with 2D Graphics Accelerator for System on Chip Solutions
Nilesh kumar agrawal · International journal of advanced electronics and communication systems · 2012
This paper proposes the implementation of the low area AMBA bus architecture and 2D graphics Accelerator interface with bridge application for SOC Solution. We have implemented an efficient hardware solution for AMBA protocol and 2D graphics Accelerator IP core optimised for minimal area requirements. The system is compartmentalized with some function modules, and they are designed by VHDL. The RTL code of Amba 2.0 and 2D graphic accelerator is simulated in Modelsim and synthesized on Xilinx vertex4 (4vlx15sf363-12) successfully and has been successfully prototyped and tested on an FPGA