Compiler-in-the-loop exploration of programmable embedded systems
Nikil D. Dutt, Aviral Shrivastava · 2006
Increasing complexity of embedded systems, and shortening time-to-market makes designer productivity the key concern in embedded system development. As a result Programmable Embedded Systems---that have a programmable processor and memory subsystem to support the software part of the application---are becoming an attractive platform for embedded system design. Programmable embedded systems greatly enhance design reuse, reduce the complexity, and time-to-market via software. The application-specific, strict, multi-dimensional design constraints, result in embedded processor designs being highly customized. Embedded processors often feature design idiosyncracies, custom-algorithms, and sometimes even miss some architectural features. Consequently, code generation for the embedded processors is a challenging task. However, if the compiler is able to exploit the architectural features of the embedded processors, it can make a tremendous difference in the power, performance, etc. of the eventual system. Existing embedded system design/exploration techniques either do not consider compiler effects on the design, or include the compiler effects in an ad-hoc manner, which may lead to inaccurate evaluation of design choices and therefore result in suboptimal design decisions. This thesis proposes a Compiler-in-the-Loop Exploration approach, a systematic method to include compiler effects during architectural evaluation of embedded systems. This dissertation demonstrates the need and usefulness of the proposed methodology at several levels of embedded system design abstraction: at the instruction set architecture level, at the processor pipeline design level, at the memory design level, and at the processor-memory interface level. At each level of design abstraction, this dissertation demonstrates that the proposed methodology results in a more meaningful exploration of design space leading to better design decisions with respect to the design goals of performance, code size, energy and power consumption.