Increasing the Code Density of Embedded RISC Applications
Hanni Lozano, M.R. Ito · 2016
Cache misses are problematic in real-time systems because they are unpredictable. Therefore, smaller codes that can fit in on-chip fast memories will help get rid of caches. However, reducing RISC applications code size is not an easy task because traditional RISC instruction sets have fixed length instructions compared to the higher density CISC instruction sets that use variable length instructions. A solution used in modern RISC processors is to combine mixed length instruction sets to achieve code densities comparable to if not higher than CISC without any performance degradation. To further enhance the code density of mixed length RISC instruction sets we add a number of 8-bit instructions to a 16-bit RISC instruction set and use novel techniques such as static compression of immediate values to compensate for the limited number of bits available for instruction encoding. The addition of 8-bit instructions combined with the proposed novel techniques reduces RISC code size by as much as 30% without degrading performance while using less than 5% additional hardware. Total processor power is reduced by 10%.