Design Of High Speed Fir Filter On Fpga By Using Multiplexer Array Optimization In Da-Obc Algorithm
Palepu Mohan Radha Devi, Vijay K. R. Chenchela, Palepu Vijayasanthi, Nellore Kapileswar · INFM-OAR (INFN Catania) · 2016
The main objective of the project is to implement FIR filter on FPGA using Distributed Arithmetic-Offset Binary Coding (DA-OBC) reduction technique. Digital filtering algorithms are most commonly implemented using general purpose digital signal processing chips for audio applications, or special purpose digital filtering chips and application- specific integrated circuits (ASICs) for higher rates. This paper describes an approach to the implementation of digital filter algorithms based on field programmable gate arrays (FPGAs). Implementing hardware design in Field Programmable Gate Arrays (FPGAs) is a formidable task. There is more than one way to implement the digital FIR filter. Based on the design specification, careful choice of implementation method and tools can save a lot of time and work. Mat Lab is an excellent tool to design filters. There are toolboxes available to generate VHDL descriptions of the filters which reduce dramatically the time required to generate a solution. Time can be spent evaluating different implementation alternatives. Computation algorithms are required that exploit the FPGA architecture to make it efficient in terms of speed and/or area. By using this algorithm, memory size can be reduced and also the speed of the operation can be increased. The FIR filter can be simulated on FPGA device by VHDL language in MODEL SIM and simulation on MATLAB is in this project.