An FPGA-Based Floating Point Unit for Rounding Error Analysis
Michael Frechtling, Philip H. W. Leong · IMPERIAL COLLEGE PRESS eBooks · 2015
Detection of floating-point rounding errors normally requires run-time analysis in order to be effective and software-based tools are seldom used due to the extremely high computational demands. In this paper we present a field programmable gate array (FPGA) based floating-point co-processor which supports standard IEEE-754 arithmetic, user selectable precision and Monte Carlo Arithmetic (MCA). This co-processor en-ables the detection of catastrophic cancellation and minimizing required floating-point precision in reconfigurable computing applications IEEE-7541 has long been the standard for computing using floating-point (FP) numbers, however, as a finite precision arithmetic system it is capable of anomalous results. Rounding error during computation can significantly reduce the accuracy of a computation, and result in errors many times