Deflection Containment for Bufferless Network-on-Chips
Xiyue Xiang, Nian-Feng Tzeng · 2016
Without buffers in its constituent routers to reduce power consumption and hardware complexity, the bufferless network-on-chip (NoC) is subject to growing deflection when the traffic load rises, leading to severe performance degradation and squandering the power-saving potential as well. This work proposes Deflection Containment (DeC) for the bufferless NoC to address its notorious shortcoming of excessive deflection for performance improvement and power reduction. With a link added to each router for bridging subnetworks (whose aggregated link width equals a given value, say, 128b), DeC lets a contending flit in one subnetwork be forwarded to another subnetwork instead of deflected, yielding extraordinary deflection reduction and greatly enriching path diversity. In addition, router microarchitecture under DeC is rectified to shorten the critical path and lift network bandwidth. We evaluate the proposed DeC design using multiprogrammed SPEC CPU2006 benchmarks and various synthetic traffic loads, for 4×4, 8×8, and 16×16 mesh-based NoCs. The results reveal that DeC comprising two bridged subnetworks can substantially contain deflection by up to 75%, yielding network power reduction by 60% and the weighted speedup of 28% averaged across all experiments.