Principle of Nand Flash Memory
2015
This chapter shows the single-cell architecture of NAND flash memory. One NAND string consists of 32 series-connected stacked gate memory transistors and two select gate transistors. The scaling of a high-voltage transistor (HV Tr) is one of the important challenges for NAND flash memories. Several program and erase schemes were considered to use a NAND flash memory product in early stage of development. There are several program boosting schemes for multilevel NAND flash cells. The first one is a conventional selfboosting (SB) scheme. The second one is a local self-boosting scheme. The third one is the erase-area self-boosting scheme (EASB). EASB was widely used for multilevel cell (MLC) to obtain a higher boosting voltage. In order to relax high electric field, the self-boosting scheme is becoming a more advanced and complicated scheme for each generation of NAND flash memory.