Parallelized Benchmark‐Driven Performance Evaluation of Symmetric Multiprocessors and Tiled Multicore Architectures for Parallel Embedded Systems*
Arslan Munir, Ann Gordon-Ross, Sanjay Ranka · 2016
In this chapter, the authors evaluate two multicore architectures for embedded systems, namely symmetric multiprocessors (SMPs) and Tilera's tiled multicore architectures (TMAs). They parallelize an information fusion application, a Gaussian elimination (GE) benchmark, a matrix multiplication (MM) benchmark, and an embarrassingly parallel (EP) benchmark for SMPs and TMAs to compare and analyze the architectures' performance and performance per watt. The authors also provide a quantitative comparison between SMPs and TMAs based on various device metrics, such as computational density (CD) and memory subsystem bandwidth. This quantitative comparison provides a high-level evaluation of the computational capability of these architectures. The SMPs depicted better scalability and performance for benchmarks requiring excessive communication and synchronization operations between operating cores, such as in the GE benchmark.