Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design
Jielin Wang, Weizhen Wang, Jianwei Yang, Zhiyi Yu, Jun Shu Han, Xiaoyang Zeng · 2015
Advanced Encryption Standard (AES) plays an important role in modern cryptographic applications. High performance implementation of AES are required for many application scenarios. Parallelization techniques are popular in recent years to improve the performance. In this paper we propose two parallel AES schemes, one is full software implementation and another is software implementation with hardware accelerator. These schemes are implemented on two 4-core clusters with shared memory architecture. The experimental results show that our parallel schemes have a good performance compared with related works and speedup for two schemes achieves 4.92 and 9.78, respectively. The throughput achieves 176.48 Mbps when using hardware accelerator.