Memory Hierarchy and Virtual Memory Management
Yamin Li · 2015
Memory is a temporary place for storing programs. It is commonly implemented with dynamic random access memory (DRAM). This chapter describes the memory structures, cache organizations, virtual memory management, and translation lookaside buffer (TLB) organizations. The mechanism of the TLB-based microprocessor without interlocked pipeline stages (MIPS) virtual memory management is also introduced. There are many types of memory, but the chapter discusses the following four types of memory: static random access memory (SRAM), DRAM, read-only memory (ROM), and content addressable memory (CAM). The parameters for designing a cache include the total cache size, block size, cache mapping methods, cache block replacement algorithms, cache write strategies in case of a cache hit, and cache write policies in case of a cache miss. The chapter explains these parameters in detail. It also gives the Verilog HDL code for a design example of an eight-entry TLB.