An optimized hardware architecture of 4×4, 8×8, 16×16 and 32×32 inverse transform for HEVC
Manel Kammoun, Emna Maamouri, Ahmed Ben Atitallah, Nouri Masmoudi · 2016
Most video coding standards use transform algorithms to reduce the size of data characterizing a video signal. The traditional transform matrices as in H.264 are limited to 4×4 and 8×8 sizes. However, the flexibility of coding structure presented in the next generation of video coding standard High Efficiency Video Coding standard HEVC allows the definition of various sizes of transform matrices which can vary from 4×4 to 32×32. This paper describes a unified hardware architecture for 4×4, 8×8, 16×16 and 32×32 inverse 2D core transform IDCT in HEVC standard. It used only one block 1D transform and a transpose buffer based on FIFO memory blocs instead of the traditional register array in order to further reduce the memory resources. The synthesis results under TSMC 180 nm CMOS technology show that the total gate count of the design is more than 30% improved compared to previous works. However, the operating frequency of the hardware design is about 130 MHz. This last can perform the decoding of 25 frames per second of Quad HD (3840×2160) resolution.