ASAP-a 2D DFT VLSI processor and architecture
J.D. Mellott, M. Lewis, Fred J. Taylor, Patrick C. Coffield · 2002
In this paper we examine the use of a recent innovation, called the logarithmic residue number system or LRNS, as an alternative to conventional DSP processors for implementing multiply-accumulate (MAC) operations. ASAP is a custom VLSI multiprocessor chip based on the LRNS. The fabricated ASAP device is capable of achieving MAC bandwidth-area ratios far greater than a conventional processor. The architecture of the ASAP device is discussed in detail as well as its application to the FFT.