On the testable design and built-in self-test of plas
Dongho Ha · 1987
In this thesis we studied testable design and built-in self-testable PLAs. Experimental results on those designs were also discussed. A new approach to the design of testable PLAs was presented. The essential idea of the design is to control individual bit lines by introducing extra pass transistors in the input decoders. The proposed design leads to testable PLAs with small area overhead and small number of tests. Several methods to reduce the size of test sets were discussed. The same design method is applied to design testable CMOS domino PLAs. Two tests called initializing inputs are applied to the CMOS PLA under test to translate all stuck open faults to equivalent line stuck-at faults. Random pattern testable (RPT) and Pseudo-exhaustive testable (PET) PLA designs that are suitable for built-in self-test environment were presented. In the proposed RPT PLAs weighted random patterns are applied to reduce the effective fan-in of input NOR gates and a group of product lines are enabled at a time to reduce that of the output NOR gates. The essence of the proposed PET PLAs is to partition the inputs and the products lines of the PLAs into groups. While testing, a group of inputs and a group of product lines are selected, and all possible input combinations are applied to the selected inputs. The proposed testable and the built-in self-testable PLA designs were applied to 56 example PLAs. The performance of the proposed designs was measured in various aspects: size of test set, area and time overhead. Experimental results show that the proposed testable design to PLAs requires small number of tests and is efficient in area compared with that of competing testable designs of PLAs. The fault coverage of the proposed RPT PLAs is improved when compared with a competing RPT PLA design. The proposed PET PLAs are more efficient in area than that of the proposed RPT PLA design and a competing built-in self-test PLA design.