Three‐Dimensional Nand Flash Cell
S. Aritome · 2015
This chapter introduces major three-dimensional (3D) cells. The bit cost scalable (BiCS) cell has a new structure of the stacked control gate layers and vertical poly-silicon channel. The thinner poly-silicon channel can obtain the easier electrostatic control performed by the gate electrode over the thinner body and the smaller poly-silicon grains which reduce the impact on the channel current of statistical variation of smaller grain size configuration. Terabit cell array transistor (TCAT) has a similar structure of BiCS, with a vertical poly-silicon channel, stacked word lines, and a silicon nitride (SiN) charge storage layer of the surrounding gate SONOS cell. The chapter describes a process sequence of vertical gate NAND (VG-NAND) cell and proposes a dual control gate with a surrounding floating-gate (DC-SF) cell for 3D NAND flash memory. This structure allows to apply floating gate to a 3D stacked cell structure with minimal cell size and high coupling ratio.