Exceptions and Interrupts Handling and Design in Verilog HDL
Yamin Li · 2015
This chapter first introduces the general mechanism for dealing with the exceptions and interrupts, including how to detect an exception and an interrupt, how to transfer control to the exception/interrupt handler, and how to return from the exception or the interrupt. A synchronous internal exception is caused by the actions of an instruction in the currently executing program. An asynchronous external interrupt is generated by external hardware devices. There are two ways to transfer control to the exception/interrupt handler: polled exception/interrupt and vectored exception/interrupt. Next, the chapter describes a single-cycle CPU that can deal with interrupt and exceptions. It also gives the test program and test data in memory initialization file (mif) format for verifying the interrupt/exception mechanism. The mif files need to be converted to hex format for the simulation with ModelSim. The Verilog HDL code and the simulation waveform of the CPU are also provided in the chapter.