Design of Pipelined CPU with FPU in Verilog HDL
Yamin Li · 2015
This chapter describes the design of a pipelined CPU which has a floating-point unit (FPU). The instructions executed by the FPU include float addition, subtraction, multiplication, division, and square root. These instructions fetch operands from a floating-point register file, rather than from the general-purpose register file which is for use by the integer unit. The chapter introduces the instructions related to the FPU and their pipeline models. It then describes the data hazards and pipeline stalls caused by the instructions related to the FPU. The contents include the data dependencies among float computational instructions; the data dependencies between lwc1/swc1 instructions and float computational instructions; and the pipeline stalls for the execution of the div.s and sqrt.s instructions. The chapter also provides the complete Verilog HDL codes of the pipelined CPU with an FPU, the test program and data, and the simulation waveforms.