High‐Performance Energy‐Efficient Multicore‐Based Parallel Embedded Computing*
Arslan Munir, Ross Gordon, Sanjay Ranka · 2016
The high-performance energy-efficient embedded computing (HPEEC) domain addresses the unique design challenges of high-performance and low-power/energy embedded computing. This chapter focuses on high-performance and energy-efficient techniques that are applicable to embedded systems (chip multiprocessors (CMPs), systems-on-chip (SoCs), or multiprocessor systems-on-chip (MPSoCs)) to meet particular application requirements. The HPEPEC domain benefits from architectural innovations in processor core layouts, memory design and interconnection networks. The chapter discusses various characteristics of embedded system applications and presents novel architectural approaches to increase performance and reduce energy consumption in parallel embedded systems. It also discusses hardware-assisted middleware techniques for performance and energy optimization of parallel embedded systems and describes software approaches for improving performance and power efficiency of a parallel embedded platform. In addition, it addresses some prominent multicore-based parallel processors and emphasizes on their HPEEC features. Finally, the chapter highlights research challenges and future research directions for HPEPEC.