A reliability aware application mapping onto mesh based Network-on-Chip
Navonil Chatterjee, Sheshivardhan Reddy, Shilpa Reddy, Santanu Chattopadhyay · 2016
Reliability aware mapping technique is an emerging area of research in Network-on-Chip (NoC) domain. As the number of Intellectual Property (IP) cores being integrated in a single chip increases, heat dissipation becomes a major issue. Due to non-uniform heat spreading, thermal hotspots are formed which reduces the system reliability. In this work, we have proposed a reliability aware mapping algorithm for application mapping onto mesh based Network-on-Chip (NoC). A cost metric is formulated that incorporates both network communication cost and system reliability, and provides an optimization objective. The mapping method uses constructive heuristic approach with integrated cost function, to generate optimized solutions depending on the requirement of the user. Experimentation with benchmarks and synthetic applications show significant improvement in system reliability and communication cost compared to other works mentioned in the literature. A comparative analysis of network performance including latency and throughput has also been reported.