Automatic analog power distribution synthesis in rail
Balsha R. Stanisic · 1993
The move to higher levels of integration has increased the fraction of application specific integrated circuit (ASIC) designs containing both analog and digital circuits. While the die area for the analog portion of these chips is modest, the design time is often significant. This has motivated the development of automated analog physical design tools for cell-level place-and-route and system-level signal-integrity-routing. To date, we are aware of no tool that has specifically addressed the critical design task of synthesizing the power distribution for the analog portion of an analog or mixed-signal ASIC. In this thesis, we describe algorithms for analog power distribution synthesis and demonstrate their effectiveness. Existing digital power bus synthesis algorithms have failed to address critical concerns for analog circuitry, thus yielding unacceptable results. These tools synthesize only the bus component of power distribution networks and only consider simplified DC aspects of macros and busses. In this research, we present a new formulation for the analog power distribution synthesis problem which synthesizes both the power busses and power I/O cell assignment by evaluating DC, AC, and transient interaction between the macros, busses, chip substrate, and package. Further, we introduce algorithms which simultaneously optimize power I/O cell assignment, power bus topology selection, and power bus sizing. RAIL, the power distribution synthesis tool developed in the course of this research, addresses many of the concerns in supplying power to analog circuits. RAIL iteratively improves the design by optimizing the power I/O cell assignment, the power bus topology selection, and the power bus sizing simultaneously via simulated annealing algorithms. With each iteration, RAIL evolves the design evaluating the static and dynamic behavior of circuits containing linearized resistors, capacitors, inductors, dependant sources, and time-varying independent sources, using Asymptotic Waveform Evaluation (AWE). We have found our formulation effective on several synthetic, industrial, and university analog and mixed-signal examples. For example, we have synthesized the analog power distribution for a 7.5mm x 7.5mm chip, consisting of 25 macrocells, modeled with 304 power bus segments, 618 electrical nodes, a 10 x 10 x 1 substrate grid to meet 361 DC, AC, and transient electrical constraints.