An energy-efficient parallel multi-core ADAS processor with robust visual attention and workload-prediction DVFS for real-time HD stereo stream
Kyuho Jason Lee, Kyeongryeol Bong, Changhyeon Kim, Jun-Young Park, Hoi‐Jun Yoo · 2016
A heterogeneous multicore processor is proposed to accelerate advanced driver assistance system (ADAS). To enable a real-time operation of ADAS functions with 720p stereo video stream, multiple granualrity parallel SIMD/MIMD architecture is proposed with precise visual attention and high throughput network-on-chip to reduce computation cost and network congestion, respectively. In addition, it employs a data resource management processor to control workload-prediction dynamic voltage and frequency scaling to reduce power consumption. As a result, the proposed SoC ahcieves 862GOPS/W energy efficiency and 31.4GOPS/mm2area efficiency, which are 53% and 75% improvement over the state-of-the-art ADAS processor, respectively.