Mars: a high-level synthesis tool for digital signal processing architecture design
Ching‐Yi Wang · 1992
In this thesis we address high-level synthesis methodologies for dedicated, real-time digital signal processing (DSP) architectures. The objective of this thesis is to develop new algorithms which can automate the process of designing dedicated DSP architectures. Before we address the synthesis of complete DSP systems, we present new algorithmic transformations which allows us to generate functional building blocks (such as adders and multipliers to obtain the desired speed requirement while minimizing the silicon area. We propose a systematic unfolding transformation technique which transforms arbitrary bit-serial architectures into functionally correct digit-serial architectures. Next we address the automatic synthesis of control circuits for DSP systems. We propose a new folding algorithm which enables us to map a set of algorithmic operations into one hardware operator while maintaining the same functionality. This algorithm also is capable of transforming bit-parallel architectures into digit-serial and bit-serial architectures. We also propose new algorithms which automatically performs the set assignment task for the control circuit synthesis algorithm when given an algorithmic DSP system. Finally we propose a new concurrent scheduling and allocation algorithm based on iterative loops for resource-constrained problems. All of these algorithms have been coded in C and have been incorporated into the MARS (Minnesota ARchitecture Synthesis) system.