Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Nano-Technology
Devendra Kumar · IOSR Journal of Electronics and Communication Engineering · 2013
Power and delay optimization is a very crucial issue in low voltage applications.In this paper, we present a design of Full Adder circuit using AVL techniques for low power operation.The approach for the design is based on XOR/XNOR & Transmission gate for single bit as hybrid design .By using this approach Full Adder is being designed using 12 transistors.We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level at supply) in which supply potential is increased.The main aim of the design is to investigate the power, Propagation Delay and Power delay Product for low voltage Full Adder for the proposed design style.The simulation results show that there is a significant reduction in power consumption for this proposed cell with the AVL technique.The circuit is designed using 65 nanometer CMOS technology and simulated using MicroWind and DSCH Ver. 3.