Comparison of FPGA implementation of LDPC encoder algorithms
Steffy Johnson, Nidhi Gaur · 2016
This paper presents the straightforward method and the lower triangular modification approach, which are the two encoding schemes for LDPC codes and compares the area utilization of both on FPGA platform. Low density parity check (LDPC) codes are linear block codes which are extensively used for error correction and detection in noisy communication channel and they discover significant application in 10GBase-T Ethernet, Wi-Fi, Wi-Max. The FPGA implementation is done on Spartan3E board and we observe that the device utilization by the straightforward method is considerably very small (only one LUT) as compared to that of lower triangular modification approach. This optimizes the size on chip as well as complexity of implementation.