Efficient Multiplier-less Design for 1-D DWTUsing 9/7 Filter Based on NEDA Scheme
Jagdamb Behari Srivastava, ey, Jitendra Kumar Jain · International Journal of Innovative Research in Computer and Communication Engineering · 2013
In this paper, we present a new efficient distributed arithmetic (NEDA) formulation of the computation of 1-D discrete wavelet transform (DWT) using 9/7 filters, and mapped that into bit parallel for high-speed and low hardware implementations, respectively. We demonstrate that NEDA is a very efficient architecture with adders as the main component and free of ROM, multiplication, and subtraction. The bit-parallel structure has 100% hardware utilization efficiency. Compared with the existing multiplier-less structures, the proposed structures offer significantly higher throughput rate and involve less area-delay product.