SSTL IO standard based power efficient data processing device design on FPGA
Diya Garg, Harsh Sohal, Sachin Ahuja · 2016
In this paper, we have designed a power efficient data center using SSTL I/O standards. We have compared the performance of our data processing device through different processors. To increase the performance, Stub-Series Terminated Logic I/O standards are used. 17 distinct functions were performed on DPD that calculated the capability of four distinct processors. At operating frequency of 1.9 GHz of AMD x2150, a significant reduction of clock power, logic power and signal power is observed as 84.47%, 45% and 41.02% respectively. Minimization in DSP power, IO power is 44.4% & 18% respectively when we apply AMD x2150 at 1.9GHz in preference to Intel Xeon E7-8893, operating at 3.4 GHz. By doing the analysis, the best results are obtained while using AMD x2150 at 1.9GHz. This paper provides a novel FPGA based design for power efficient data processing device.