Transaction Level Modeling of Processor Based on UVM
Yingke Gao, Li Quanquan, Qi Wang, Tiejun Zhang, Donghui Wang, Chaohuan Hou · International Conference on Electronics, Communications and Control · 2012
As the complexity of integrated circuit increases, the transaction level model (TLM) bridges the architecture and the hardware implementation. With SuperV DSP as the research prototype, this paper presents a new method to implement the transaction level model based on UVM, which provides plenty of System Verilog libraries. This model can accelerate software development and be used as a golden reference model in the verification of RTL model without complex interface function.