Notice of Violation of IEEE Publication Principles - Super-scale architecture enhancement of LEON3 core for DSP application
Jagrat Mehta, Anand D. Darji, Tulchhi Ram, Rajat Arora · 2015
Notice of Violation of IEEE Publication Principles"Super-Scale Architecture Enhancement of LEON3 Core for DSP Application"By Jagrat Mehta, Anand Darji, TVS Ram, Rajat Arorain the Proceedings of the 19th International Symposium on VLSI Design and Test (VDAT), June 2015After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles.This paper contains substantial duplicate text from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission.Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article:"Enhanced LEON3 Core for Superscalar Processing"by Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A. Pleskaczin the Proceedings of the 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, (DDECS), April 2009, pp. 238-241There are two main directions in the development of modern microprocessor architectures used for System on Chip: low Power consumption and high performance. The paper presents the method for enhancing LEON3 processor IP core with superscalar ability for high-performance and low-power systems. As compared to the original LEON3 IP core, the proposed super scalar design executes is up to two instructions per cycle with only one third area increase. Application to perform FFT/IFFT is developed and tested using enhanced architecture of LEON3 IP core for superscalar processing. Performance enhancement of LEON3 core is also compared with Very Long Instruction Word (VLIW) processor and Silicon labs application note. The enhanced SoC is synthesized and implemented on Actel FPGA ProASIC3E. The area, power and timing comparison is shown. Approximately 33% enhancement in execution time is obtained due to the proposed super scaling scheme for LEON3 IP core.