An ILP-based floorplan-aware path synthesis technique for Application-Specific NoC design
Priyajit Mukherjee, Santanu Chattopadhyay · 2016
In Application-Specific Networks-on-Chip, both positions of the routers and the routes for each communication trace in the Core Graph can be adjusted to suit a particular application. For an application, input to the current work is a gridded floorplan having the fixed positions of cores and a set of routers in it. Maximum physical link length between two routers is also considered as a constraint. For each edge in the Core Graph, corresponding to an application, the proposed method selects a particular path from all possible paths, between two grid points. In this way, a set of paths is constructed for all edges in the Core Graph to minimize the communication cost of the design. This work also inserts junction routers at the junctions of two paths and secondary routers or repeaters on a long link, to sustain a pre-specified maximum link length. We have proposed an Integer Linear Programming formulation for path synthesis and a heuristic approach to generate alternative paths. The proposed method is tested with benchmark applications and compared with shortest path based greedy approaches. The results show an immense improvement in average packet latency and throughput using our method.