Floating‐Point Algorithms and FPU Design in Verilog HDL
Yamin Li · 2015
In the modern CPUs, there is a floating-point unit which can operate on floating-point numbers. The IEEE 754 Standard defines mainly two floating-point formats, float and double. The conversions between floating-point numbers and integers are common operations in software development. This chapter presents the converter design in Verilog HDL and gives the simulation waveforms. It then describes the design of an adder that can perform addition or subtraction on IEEE 754 single-precision floating-point numbers. Next, the chapter presents the algorithm of floating-point multiplications, the design of a float multiplier with Wallace tree, and the design of a pipelined float multiplier. It also describes the float division algorithm and the design of the float divider which uses the Newton-Raphson algorithm to implement the significand division. Finally, the chapter presents the algorithm and design of the float square rooter which uses the Newton-Raphson algorithm to implement the significand square root.