A Residue Number System Based Time-to-Digital Converter Architecture and its FPGA Implementation
Cong Bing Li, Haruo Kobayashi · Key engineering materials · 2016
A time-to-digital converter (TDC) based on residue number system is presented. This architecture can reduce hardware and chip area as well as power significantly compared to a flash-type TDC while keeping comparable performance. Its proof-of-concept prototype was implemented on FPGA, and the measurement results validate the effectiveness of the proposed architecture