Logic synthesis for self-checking VLSI design
F.Y. Busaba · 1993
On-line testing, also known as concurrent checking, enhances the reliability of VLSI (Very Large Scale Integration) circuits. A circuit with concurrent checking capability is known as self-checking. Such a circuit can detect fault(s) in itself during its normal operation. Currently available error detection schemes can detect faults that create unidirectional errors at the output. A circuit designed using the conventional approach can produce bidirectional errors in the presence of a fault. In this dissertation, we present techniques for designing arbitrary combinational circuits so that any single stuck-at fault will only result in either a single bit error or unidirectional multibit errors at the output. An input encoding algorithm and an output encoding algorithm that ensure that every fault at the input will either produce a single bit error or unidirectional multibit error at the output are proposed. The proposed techniques have been applied to MCNC benchmark circuits and the overhead has been estimated. A technique for designing state machines which are totally self-checking for single stuck-at faults has been presented. State assignment in a sequential machine can be viewed as an input and/or output encoding problem. Therefore, the input and output encoding schemes developed for combinational circuits can also be applied to the next state logic (NSL) and the output logic (OL) of a finite state machine. This technique for self-checking design has been applied to MCNC benchmark circuits and the overhead has been estimated. Complex state machines are often implemented such that they are composed of smaller interacting submachines. In such a structure, even if each of the interacting submachine is self-checking, it is not guaranteed that the composite machine will be self-checking. This is due to the limited controllability/observability of the intermediate lines between the submachines. A technique for designing interacting finite state machines which will be totally self-checking for any single stuck-at fault is developed in this dissertation. Finally, a modified version of the above technique for designing self-checking interacting machines in the presence of multiple stuck-at faults is proposed. The modified technique assumes that each submachine can have only one single stuck-at fault although more than one submachine have single fault.