Implementation and Analysis of Modified Double Precision Interval Arithmetic Array Multiplication
Krutika Ranjankumar Bhagwat, Tejas V. Shah, Deepali H. Shah · 2012
This paper presents the design of a 64 bit array multiplier that performs interval multiplication. This multiplier requires carry save adders instead of full adders that reduces the delay i n r e s p e c t o f conventional array multiplier. The 64 bit multiplication requires 53 x 53 multiplication which is done by array multiplier it has n*(n-1) CSA, where n=53 so, n*(n-1) = 53 *52= 2756 CSA is used. Arrangement of 2756 CSA is used to add partial products of multiplier. This multiplier is based on interval arithmetic which provides the better accuracy, b y removing rounding off error over conventional floating point multiplier. There is performance improvement over software implementation of interval arithmetic, but it requires slightly more area rather than conventional floating point unit.