Architectures for the three-dimensional discrete wavelet transform
Michael Clark Weeks, Magdy Bayoumi · 1998
Volumes of 3-D data, such as Magnetic Resonance Imaging (MRI), desperately need compression. The 3-D Discrete Wavelet Transform (DWT) suits this application well, to give it maximum compression without blocking artifacts. This dissertation compares VLSI architectures for the Discrete Wavelet Transform (DWT) and presents 2 new architectures. Many architectures for the Discrete Wavelet Transform (DWT) have been proposed since 1990. The DWT is not a straight-forward problem to implement on a chip, so there are several types of designs. The types of architectures depend on the application data's dimensions, and the algorithm used, as well as whether the design is systolic, semi-systolic, folded, or digit-serial. The advantages and disadvantages of each design will be presented in this work. Medical applications are the targets for the 3-D Discrete Wavelet Transformers. MRI studies generate multiple megabytes of data, and MRIs are of reasonable X and Y dimensions, and have grey-scale values for pixels, so the data precision (8 bits) is also low. Television applications may also be on the horizon for this technology. The first architecture is an implementation of the 3-D DWT similar to 1-D and 2-D designs. It allows even distribution of the processing load onto 3 sets of filters, with each set doing the calculations for one dimension. The filters are easily scalable to a larger size. The control for this design is very simple, since the data are operated on in a row-column-slice fashion. The design is cascadable. Due to pipelining, all filters are utilized 100% of the time, except for the start up and wind-down times. The second architecture uses block inputs to reduce the amount of on-chip memory. It has a control unit to select which coefficients to pass on to the low and high pass filters. The memory on the chip will be small compared to the input size, since it depends solely on the filter sizes. The filters are parallel, since the systolic filters assume that the data is fed in a non-block form such that partial calculations are done. These 2 new architectures are some of the first 3-D DWT architectures.