Schedule-clock-tree routing for semi-synchronous circuits
Kazunori Inoue, Wataru Takahashi, Atsushi Takahashi, Yoji Kajitani · Tokyo Tech Research Repository (Tokyo Institute of Technology) · 1999
It is known that the clock-period can be shorter than the maximum of signal-delays between registers if the clock arrival time to each register is properly scheduled.The algorithm to design an optimal clock-schedule was given.In this paper, we propose a clock-tree routing algorithm that realizes a given clock-schedule using the Elmore-delay model.Following the deferred-merge-embedding (DME) framework, the algorithm generates a topology of the clock-tree and simultaneously determines the locations and sizes of intermediate buffers.The experimental results showed that this method constructs a clocktree with moderate wire length for a random layout of scheduled registers.Notably, the required wire length for a gentle layout of scheduled registers was shown to be almost equal to that of zero-skew clock-trees.