Implementation of Low Power Digital Clock Design Using Capacitance Scaling On FPGA
Shubham Gargrish, Harsimran Jit Kaur, Payal Tanwar · International Journal of Urban Design for Ubiquitous Computing · 2014
In this paper, we are designing digital clock using Xilinx ISE 14.2 and implementing it on high performance virtex-6 FPGA; Verilog HDL is used to synthesize the clock on FPGA; FPGA is taken as target device. The power consumption of FPGA based digital clock has been verified using Xilinx 12.1 tool. A 7-Segment LCD display has been used for displaying the output. Further power consumption has been reduced by efficiently scaling the capacitance value. When device is in use on 50MHz, 100MHz and 300MHz frequency the diminution is achieved by mapping the value of capacitance.