Effective Partial Reconfiguration of Logic Controllers Implemented in FPGA Devices
Remigiusz Wiśniewski, Monika Wisniewska, Marian Adamski · Studies in systems, decision and control · 2015
A method of partial reconfigurationReconfigurationpartial of logic controllersLogic controllerreconfigurable (RLC) implemented in FPGAFPGA is presented in the chapter. Only the control memoryControl memorymemory content is replaced while the rest of the system is not modified. The logic synthesisLogic synthesis and implementationImplementation are performed only once. Therefore, such a realisation highly accelerates the whole prototyping process. The performed experiments showed that the original bit-stream that is sent to the FPGAFPGA can be reduced even over 500 times.