A mixed-mode vlsi implementation of artificial neural networks for character recognition
M.I. Elmasry, Joshua A. Hanson, Sameh Ebrahim Rehan · 1995
Dedicated VLSI circuits, which provide a compact implementation and a fast processing of artificial neural networks (ANNs), can release the full power of ANNs. In this thesis, a combined top-down bottom-up VLSI design methodology is proposed for implementing ANN chips that can be used for character recognition. An XOR ANN chip is implemented and tested to demonstrate the main steps of the proposed VLSI design methodology. A new incremental-learning procedure, which demonstrates more tolerance towards input noise than the standard procedure, is introduced. A mixed-mode switched-resistor (SR) VLSI implementation of ANNs is presented. A chip containing a novel programmable SR synapse as well as a simple CMOS analog neuron is designed, fabricated, and tested. An extended MLP model architecture is proposed to solve multi-character recognition problems. A parallelogram VLSI architecture is developed to implement the ANN circuit of the extended MLP. A complete multi-chip multi-character ANN recognition system is proposed. ANN model, behavioral, and circuit simulations are performed for three prototype multi-layer perceptron (MLP) model architectures. The first MLP solves the XOR problem, the second MLP works as a two-character recognizer, and the third MLP is designed as a multi-chip three-character ANN recognition system. This research demonstrates the feasibility of an SR CMOS VLSI implementation of ANNs for character recognition.