28nm generation programmable families
Brad Taylor, Ralph Wittig · 2010
▪ Unified device architecture for all 7 Series FPGAs - Scalable platform with three families: cost, power, performance - 50% total power reduction - Increased capacity and bandwidth ▪ Xilinx EPP: SOC with embedded programmable logic array - Boots like a processor - SW centric programming model - Extensible peripheral set and compute ▪ All Xilinx IP (soft and hard) use AMBA AXI interconnect - High performance, scalable interconnect - AXI4 is optimized for FPGAs - Memory mapped and streaming interfaces ▪ Availability - IP with AXI interface: Sept 2010 - 7 Series FPGAs: First devices in early 2011 - EPP: To Be Announced