The IBM power edge of Network™ processor: A wire-speed system-on-a-chip with 16 Power™ cores / 64 threads and optimized HW acceleration
Jeffrey D. Brown, Sandra Woodward, Brian Bass, Charlie Johnson · 2010
Presents a collection of slides covering the following topics: Network processor; IBM power edge; wire-speed system-on-a-chip; interconnect architecture; PowerPC processing element architecture; DDR3 DRAM controller; accelerator architecture; accelerator interface; compression/decompression; crypto data mover; XML engines; packet processor architecture; and PCI-Express.