Advanced Hardware Optimization Algorithms for High Performance Queue Processor Architecture
Hiroki Hoshino · 2009
Instruction level parallelism (ILP) is important to improve performance of general processors. ILP allows the instruction of a sequential program to be executed in parallel. However aggressive optimization of the compiler and some bigger hardware mechanisms are needed to find and exploit ILP. In this research the queue based instruction set architecture is used. This architecture o ers an attractive option in the design of embedded systems. Instructions based on queue machine are generated using level order traversal that allows us to find all available parallelism in programs. Thus the hardware executes instructions in parallel with little e ort. Some optimization and design issues for queue processor architecture (QC) have been proposed. This processor implemented the o set references, the memory extension instruction, the pipelined structure and the floating point execution unit. However the optimized QC cannot reuse data in the queue register. Also, if the queue register is full of available data, there is the critical problem that the processor cannot execute any more. This research describes the solution of problems such as the reusing data problem and the queue register overflow problem.