Mixed-criticality scheduling with memory regulation
Muhammad Ali Awan, Konstantinos Bletsas, Pedro F. Souto, Benny Åkesson, Eduardo Tovar, Jibran Ali · Euromicro Conference on Real-Time Systems · 2016
The state-of-the-art models and schedulability analysis for mixed-criticality multicore systems overlook lowlevelaspects of the system. To improve their credibility, we therefore incorprate, in this work, the effects of delays from memory contention on a shared bus. Specifically, to that end, we adopt the predictable memory reservation mechanism proposed by the Single Core Equivalence framework. Additionally, we explore how the reclamation, for higher-criticality tasks, of cache resources allocated to lower-criticality tasks, whenever there is a criticality (mode) change in the system, can improve schedulability. Mixed-criticality scheduling with memory regulation Muhammed Ali Awan∗, Konstantinos Bletsas∗, Pedro Souto†∗, Benny Akesson∗, Eduardo Tovar∗, Jibran Ali∗ ∗CISTER/INESC-TEC, ISEP/IPP, Portugal †Faculty of Engineering, University of Porto, Portugal Abstract—The state-of-the-art models and schedulability analysis for mixed-criticality multicore systems overlook low-level aspects of the system. To improve their credibility, we therefore incorprate, in this work, the effects of delays from memory contention on a shared bus. Specifically, to that end, we adopt the predictable memory reservation mechanism proposed by the Single Core Equivalence framework. Additionally, we explore how the reclamation, for higher-criticality tasks, of cache resources allocated to lower-criticality tasks, whenever there is a criticality (mode) change in the system, can improve schedulability.The state-of-the-art models and schedulability analysis for mixed-criticality multicore systems overlook low-level aspects of the system. To improve their credibility, we therefore incorprate, in this work, the effects of delays from memory contention on a shared bus. Specifically, to that end, we adopt the predictable memory reservation mechanism proposed by the Single Core Equivalence framework. Additionally, we explore how the reclamation, for higher-criticality tasks, of cache resources allocated to lower-criticality tasks, whenever there is a criticality (mode) change in the system, can improve schedulability.