A Negative Word-line Voltage Step-Down Erase Pulse Scheme with ΔVTH=⅙ ΔVERASE for Enterprise SSD Application Ferroelectric(Fe)-NAND Flash Memories
Ryoji Yajima, T. Hatanaka, Mari I. Takahashi, Shigeki Sakai, Ken Takeuchi · 2009
2009 International Conference on Solid State Devices and Materials,A Negative Word-line Voltage Step-Down Erase Pulse Scheme with ΔVTH=⅙ ΔVERASE for Enterprise SSD Application Ferroelectric(Fe)-NAND Flash Memories