Architecture and design of a new memory test synthesis framework
Shambhu Upadhyaya, Kamran Zarrineh · 1999
This dissertation is aimed at the generation of a complete memory test synthesis framework to facilitate quick design time-to-market for today's memory-intensive systems. The objectives are accomplished by developing a new test generation and compaction scheme and implementing it in a comprehensive framework. The essential components of our framework are: the automatic generation of march tests to address memory faults, the architecture of programmable memory Built-In Self Test (BIST) units and the automatic generation, insertion, and verification of memory BIST units. The dissertation also addresses the generation of easy-to-test memory blocks by adding two new parameters, time to test a memory and memory test strategy, to the traditional memory synthesis approach. A novel memory synthesis approach based on a branch and bound technique has been developed to transform logical memories to mappable memories in a design. The proposed algorithm uses the new test parameters to realize a logical memory with a set of physical memories which could be tested within the specified test time using the specified memory test strategy. An automatic memory march test generation framework has been designed and implemented to satisfy the testing requirements of custom memory faults. An effective and efficient programmable memory BIST architecture has been developed to allow the same memory BIST unit to be re-used to satisfy varying test requirements of memories in different stages of their fabrication. In this dissertation, we describe the details of a framework for automatic generation, insertion, and functional verification of full custom memory BIST units. A gate-level verification framework consisting of a structural, functional, and diagnostics frameworks has been developed. The structural verification framework is used to verify the correct functioning of the isolation logic and the interconnection of the memory BIST unit in a design. The proposed gate-level functional verification framework performs a more comprehensive verification of the correct functioning of the memory BIST unit. The proposed diagnostics verification framework ensures the correct functioning of the diagnostics logic in the memory BIST unit.